`timescale 1ns/1ns

module uart1_tb;

reg clk, reset;

wire in;

reg [65:0] data;

assign data = { 
	8'hFF,						// 8
	1'b0, 8'hAA, 1'b1,			// 10
	1'b0, 8'hAA, 1'b1,			// 10
	8'hFF,						// 8
	1'b0, 8'hAA, 2'b0, 1'b1,	// 12, error byte
	1'b0, 8'hAA, 1'b1,			// 10, ok byte
	8'hFF						// 8
};

assign in = data[65];

uart1 uut (
    .clk(clk),
    .in(in),
    .reset(reset)
);

integer i;

initial begin
    clk = 1'b0;

    reset = 1'b0;
    @(posedge clk);
	reset = 1'b1;
    @(posedge clk);
	reset = 1'b0;

	for (i = 0; i < 10000; i = i + 1) begin
		@(posedge clk);
		data <= { data[64:0], data[65] };
	end
end

always #1 clk = ~clk;


endmodule
